1. Field of the Invention
The present disclosure relates to a method of fabricating semiconductor devices, and particularly to a method of fabricating semiconductor devices including PMOS devices having embedded SiGe (eSiGe).
2. Description of the Related Art
In order to meet the demand of users for low profile electronics, in enhanced Very Large Scale Integration (VLSI) processes, stress engineering has been used to improve the performance of devices. One of the effective ways to increase hole mobility in the channel region of a PMOS device is by embedding SiGe (eSiGe) structures. In sigma-shaped (Σ-shaped) eSiGe structures, a specially shaped recess is formed and refilled with SiGe forming source and drain regions to increase stress in the channel region since the lattice constant of SiGe is larger than that of Si and the distance between source and drain regions is reduced by using the Σ-shaped SiGe.
A prior art method of forming Σ-shaped SiGe in a PMOS device is shown in FIG. 1A to FIG. 1D. After forming on a Si substrate a gate and sidewall spacers on opposite sides of the gate (FIG. 1A), a recess is formed between two adjacent gates in the Si substrate by dry etching, as shown in FIG. 1B. The section of the recess shown in FIG. 1B is a substantial rectangle with a planar bottom, which is defined by four vertices A, B, C and D.
Next, as shown in FIG. 1C, the rectangular recess is wet etched in an orientation selective manner to be expanded into Σ-shape. Commonly, orientation selective wet etching is faster on (100) crystal orientation planes than on (111) crystal orientation planes. In fact, orientation selective wet etching substantially stops on (111) crystal orientation planes. As a result, two vertices C and D formed after the dry etching shown in FIG. 1B remain as etch stop points of (111) crystal orientation planes. Finally, as shown in FIG. 1D, SiGe is epitaxially grown in the resulting Σ-shaped recess, so as to form SiGe source and drain regions.
However, conventional method of forming Σ-shaped SiGe suffer from the problem of difficult SiGe epitaxial growth. Specifically, in the dry etching process performed on the substrate shown in FIG. 1B, defects such as Si lattice mismatch or the like may occur at the edges of the formed rectangular recess, particularly at the vertices C and D shown in FIG. 1B, due to plasma bombardment. As mentioned above, as a result of orientation selective wet etching, the vertices C and D will not etch as they are (111) crystal orientation etch stop points. In the subsequent SiGe epitaxial growth, the seed layer is very sensitive to Si surface conditions, such as cleanness and Si lattice condition. Defects such as Si lattice mismatch may lead to the difficulty in the epitaxial growth of a seed layer. Hence, as shown in FIG. 1E, Si lattice defects at points C and D will make the subsequent defect free epitaxial growth of a SiGe seed layer difficult to achieve.